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New Potential for Mass Production of the Next Generation Power Semiconductor Material Six inch SiC Wafers Achieved with Zero Defects New proprietary surface nano control process developed by Kwansei Gakuin University and Toyota Tsusho


Kwansei Gakuin University and Toyota Tsusho Corporation have developed a new surface nano process technology called Dynamic AGE-ing that neutralizes defects of impurities on Silicon Carbide (SiC) wafers, which represent the next generation of power semiconductor material. This revolutionary new technology achieves both high quality and increased productivity for SiC wafers, which are expected to serve as the next generation replacement for Si wafers, currently the most common material used for power semiconductors. The technology achieves zero production defects by neutralizing defects in the wafer. With the completion of performance testing of the technology applied to six inch SiC wafers, production of a sample supply of wafers will begin in early 2021. Meanwhile, testing will begin on applying the technology to mass production lines for commercial application in cooperation with semiconductor manufacturers, while development to apply the technology to larger eight inch SiC wafers will also accelerate.

President Osamu Murata (right) and Professor Tadaaki Kaneko of Kwansei Gakuin University(left) (Provided by Public Relations Office of Kwansei Gakuin University)

An online press conference to announce the new technology was given by President Osamu Murata and Professor Kaneko of Kwansei Gakuin University on March 1. Murata emphasized the importance of the development, saying, "Professor Kaneko has been working on this technology for 20 years, and Toyota Tsusho has been involved in its joint development for the past several years. Kwansei Gakuin University has registered the trademark for the name Dynamic AGE-ing. SiC power semiconductors will exercise their strengths as the next generation in semiconductors, for use in automobiles, trains, and industrial equipment. If the Dynamic AGE-ing technology can be used for practical applications, it will enable a major leap forward in terms of quality and productivity for SiC wafers, which are already seeing an expansion in use. This will lead to a stable supply of high quality SiC wafers, which will further accelerate the use thereof in green innovation domains, such as electric vehicles (EVs). It will also enable the reduction of electricity consumption, making a major global contribution to such issues as climate change."


Until now, an issue facing SiC wafers was the serious loss in the performance of the power semiconductors formed on them due to crystal deformation (strained layer) and internal defects such as basal plane dislocation (BPD).


The process by which SiC wafers are manufactured begins with growing a large piece of crystal (an ingot), and the problem of BPD occurs at this stage. If the crystal is then sliced to make SiC wafers on which power semiconductors are formed and then sold as a product, subsequent powering up can further exacerbate the defect, causing the power semiconductor to function incorrectly, leading to catastrophic results.


Furthermore, machining processes to create SiC wafers, such as slicing, grinding, and polishing using diamond bits, can destroy parts of the crystal on the wafer surface (processing strain layer), and this phenomenon can reduce yield when producing power semiconductors for sale. Unfortunately, no technology has yet been adequately established to deal with these issues.


In response, Dynamic AGE-ing is a nano process that uses crystal growth to neutralize the BPD by changing it into threading edge dislocation, while using thermal etching to remove the processing strain layers.


Kaneko explains the characteristics of the system, saying "Unlike standard fabrication technology, this is a contactless surface nano process that combines both thermal etching and crystal growth on the SiC wafer. The SiC wafer is placed in a gas phase environment at temperatures of between 1,600 and 2,100 degree Celsius in a single process device, and the temperature is changed for autonomous control of the atomic arrangement on the crystal surface. The use of this technology can not only improve the quality of the SiC wafers, it can also simplify the manufacturing process and improve yield irrespective of size or manufacturer, resulting in improved production."


He further explained that when the technology was actually applied to an SiC wafer with over 7,000 BPD per square centimeter and then examined to see the extent to which they were neutralized, the results showed that they had reduced the number of BPD to less than one for the entire wafer surface.

This article has been translated by JST with permission from The Science News Ltd.( Unauthorized reproduction of the article and photographs is prohibited.

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