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Next-generation non-volatile memory: Functional demonstration of SOT-MRAM

2022.01.18

An international research team led by Associate Professor Pham Nam Hai of the Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, and Professor Kang L. Wang of the Department of Electrical and Computer Engineering, and Department of Physics and Astronomy, University of California, Los Angeles, has created spin-orbit torque magnetoresistive RAM (SOT-MRAM) devices that integrate topological insulators and magnetic tunneling junctions (MTJs). Readout via relatively high tunneling magnetoresistance effect and writing using low current density by a topological insulator were successfully demonstrated.

SOT-MRAM is a next-generation non-volatile memory technology that can write at a high-speed using a pure spin-current due to the spin Hall effect. To reduce the write current and power, a topological insulator with a strong spin Hall effect can be used. However, a technique that allows integration between the topological insulator and the MTJ has not been established thus far.

During the fabrication of the SOT-MRAM device, the team placed a (Bi, Sb)2 Te3 topological insulator formed using the molecular beam epitaxial crystal growth method or a BiSb topological insulator formed by a sputtering method suitable for industrial production on the lower electrode. In addition, the Ru(5 nm) with a crystallographic structure similar to that of a topological insulator was prepared as an interlayer, on which MTJs of CoFeB (2.5 nm)/MgO (2 nm)/ CoFeB (5 nm) were deposited. Next, heat treatment was performed at temperatures between 250 and 300 ℃ to crystallize CoFeB in the magnetic layer. Finally, the three-terminal SOT-MRAM devices were fabricated.

The device achieved a relatively high resistance change of 90%, despite the heat treatment of the MTJ with the integrated topological insulators at 250 ℃. In addition, the device succeeded in writing with a low current density using the spin orbit torque. This experiment helped demonstrate that topological insulators and MTJs can be integrated, and that the principal operation of read and write can be accomplished. Associate Professor Pham Nam Hai stated, "We expect that the results of this study will accelerate the research and development (R&D) of ultra-low power SOT-MRAM devices utilized in the industrial world. If these SOT-MRAM devices can be realized, we will be able to significantly reduce the power consumption in electronic circuitry."

Microscopic picture of a patterned SOT-MRAM device, where the topological insulator layer serves as the bottom electrode. The magnetic tunnel junction on top of the topological insulator layer is 2 μm×6 μm in size.
Provided by Tokyo Institute of Technolohy

This article has been translated by JST with permission from The Science News Ltd.(https://sci-news.co.jp/). Unauthorized reproduction of the article and photographs is prohibited.

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