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NTT, Nagoya University, and the University of Tokyo developed the world's first quantum error correction method in the extremely low-temperature environment required for superconducting quantum computing, with the power consumption, mounting scale, speed, error correction performance, and other factors satisfying the level required to control a quantum computer on a practical scale. This achievement is expected to contribute significantly to the development of error-tolerant quantum computers, for which competition is intensifying worldwide. The three participating organizations intend to demonstrate that quantum error correction in quantum computers is experimentally possible by concretely mounting the results of the designed research on a chip. In addition, based on the resulting design, they plan to tackle issues such as expanding it to support a mechanism that operates with logical qubits composed of surface codes.

A bit, which is a general (classical) computer element, takes a value of 0 or 1, whereas a quantum bit, which is a quantum computer element, can take a continuous superposition state of both states. This state can be used to execute calculations when the bit values are 0 and 1, but when observing a qubit, the value is fixed at 0 or 1, and the state of the superposition is broken. Qubits are prone to errors, and error correction is required in quantum computer calculations; however, owing to this property, it is not possible to directly observe the qubits and check for errors.

Due to this, a framework called a quantum error correction code has been proposed in which a plurality of physical qubits having different roles are encoded to form a single logical qubit. One of its representatives is the surface code. It consists of regularly aligned data quantum bits and auxiliary quantum bits for observation. Data qubits are used to represent the superposition state of logical qubits and are not directly observed. However, the observed values of the auxiliary qubits provide hints regarding errors that occur in adjacent data qubits. Identifying the type and location of the error that actually occurs in the data qubit from these hints is called decoding. It is known that this surface code decoding process results in a graph matching problem, and an error-tolerant quantum computer can be constructed by combining a qubit with a general computer called a decoder that solves the matching problem.

There are several known methods for realizing qubits, but among them, superconducting qubits are promising as the first candidate for quantum computer elements owing to their high integration potential and high degrees of freedom in terms of design. This superconducting qubit has a restriction that it operates in an extremely low temperature environment, and it is generally operated in a dilution refrigerator. By contrast, quantum error correction code decoders generally operate at room temperature, and thus the large amount of wiring between different temperature environments connecting the qubit and the decoder becomes a bottleneck, limiting the scalability of superconducting quantum computers. Because the power consumption allowed in an extremely low-temperature environment is quite small, it is unrealistic to operate a normal decoder in an extremely low-temperature environment.

Therefore, in this study, the research group designed a surface code decoder that can operate in an extremely low-temperature environment using a single flux quantum (SFQ) circuit that operates at high speed and with low power consumption. It was shown that the designed decoder operates at a sufficiently high speed, and when an error occurs in the qubit, it is corrected immediately, allowing an online decoding that prevents the accumulation of errors. Using this method, it is possible to reduce the wiring between different temperature environments and dramatically improve the expandability of quantum computers. Online decoding also improves the error tolerance of the qubits.

Through this joint research, the University of Tokyo examined the design of algorithms and chip mounts, and the feasibility of wiring with qubits. NTT organized the theoretical aspects of quantum error correction and evaluated the performance of the decoder, and Nagoya University conducted the chip mounting and performance evaluation at the time of mounting. As the most important point of this research idea, the decoder was constructed using the SFQ circuit through a coordinated design at the algorithm and hardware levels. They devised a graph matching algorithm of a distributed processing method when considering the locality of the processing required for decoding the surface code and the characteristics of the SFQ circuit, and designed a decoder to execute it. The designed decoder does not require a large-scale memory, and it has a structure in which simple processing units corresponding to each auxiliary qubit exchange signals of several bits. It can operate with low power consumption and achieve excellent expandability.

In addition, for the first time, they proposed a decoding method, called an "online processing method," that simultaneously observes and decodes auxiliary qubits that can operate in a realistic environment, as well as its concrete implementation. In a superconducting quantum computer, the observation process of auxiliary qubits is repeated at intervals of approximately 1 μs (1 microsecond). However, it was shown that the decoder proposed by the three parties can execute the decoding process in less than 1 μs and has the high speed required for online processing. The design of a large-scale quantum computer that can be used in actual applications has been the biggest problem in quantum computing thus far. In particular, the error correction decoder needs to be designed to process algorithms that are becoming increasingly complex as the scale of quantum computers grows at high speed. Therefore, this was one of the most difficult parts to design for an entire quantum computer.